The present disclosure relates to virtual multi-processor systems to operate a plurality of logic processors in a pseudo-parallel manner by a physical single processor.
So-called virtual multi-processor systems in which a plurality of processors are not physically provided, but a plurality of logic processors are operated virtually in a pseudo-parallel manner by a single processor have been known (for example, see Japanese Patent Publication 2003-271399). Japanese Patent Publication 2003-271399 describes an example of virtual multi-processor systems in which when on an logic processor, an interrupt specific to the logic processor is caused, an execution period in a subroutine dedicated to interrupt processing is included in an execution period (time slice) of the interrupted logic processor.